The present invention relates generally to integrated circuit memory devices and, more particularly, to a synchronous dynamic random access memory (SDRAM) system.
Problems in state of the art memory systems have been because of intrinsic delays associated with memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies, where non-zero latencies for read and write operations are the norm. In the case of ‘read’ operations, this data latency will be directly associated with the amount of time required to access the data from the sense amplifier latch or other intermediate storage location—typically 3 or 4 clocks at a 266 MHz clock speed. In the case of ‘write’ operations, whereas it is still theoretically possible to provide data and address at the same time, data will typically be delayed several clocks after address, to improve command/address bus efficiency and reduce SDRAM power—since read and write operations will generally be intermixed in the system command stream.
Due to the use of various forms of error correction code (ECC) now widely used on the data bus in server and workstations, most memory failures now result from causes other than traditional data corruption (soft and hard fails of the memory cell or supporting circuits). With the increased dependency on data storage in remote systems (databases, workrooms, department and company servers, and the internet in general), memory failures in server platforms are undergoing increased scrutiny in an attempt to minimize the time in which data or the entire system is unavailable due to hardware failures. Analysis of recent memory failure reports clearly points to the key contributors of memory-induced unplanned system outages as being related primarily to address, control, clock or related signals that do not include ECC coverage, and due to one or more of the following failure modes: connector/contact failures, memory controller or re-drive failures, high resistance solder joints, or the like. Since these signals are quite numerous, often passing through several levels of interconnects, and due to the general use of low-cost connectors, the interconnect systems are generally deemed as a significant contributor of memory failures in a well-architected ECC-protected system (representing 50% or more of total hard memory fails).